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CY7C1368C
9-Mbit (256K x 32) Pipelined DCD Sync SRAM
Features
* Registered inputs and outputs for pipelined operation * Optimal for performance (Double-Cycle deselect) -- Depth expansion without wait state * 256K x 32-bit common I/O architecture * 3.3V core power supply (VDD) * 2.5V/3.3V I/O power supply (VDDQ) * Fast clock-to-output times -- 2.8 ns (for 250-MHz device) * Provide high-performance 3-1-1-1 access rate * User-selectable burst counter supporting Intel(R) Pentium(R) interleaved or linear burst sequences * Multiple chip enables for depth expansion: Three chip enables for A package version and Two chip enables for AJ package version * Separate processor and controller address strobes * Synchronous self-timed writes * Asynchronous Output Enable * Available in JEDEC-standard lead-free 100-Pin TQFP package * "ZZ" Sleep Mode option
Functional Description[1]
The CY7C1368C SRAM integrates 256K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWA, BWB, BWC, BWD, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle. This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penal izing system performance. The CY7C1368C operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
250 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.8 250 40 200 MHz 3.0 220 40 166 MHz 3.5 180 40 Unit ns mA mA
Notes: 1. For best-practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com. 2. CE3 is for A version (3 Chip enable option) only.
Cypress Semiconductor Corporation Document #: 38-05686 Rev. *F
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 14, 2006
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CY7C1368C
Functional Block Diagram-CY7C1368C (256K x 32)
A0,A1,A
ADDRESS REGISTER
2 A[1:0]
MODE ADV CLK
BURST LOGIC
Q1
COUNTER AND
CLR ADSC ADSP BWD DQD BYTE WRITE REGISTER DQc BYTE WRITE REGISTER DQB BYTE WRITE REGISTER DQA BYTE WRITE REGISTER ENABLE REGISTER
Q0
DQD BYTE WRITE DRIVER DQC BYTE WRITE DRIVER DQB BYTE WRITE DRIVER DQA BYTE WRITE DRIVER
MEMORY ARRAY SENSE AMPS
BWC
OUTPUT REGISTERS
OUTPUT BUFFERS
E
DQs
BWB
BWA BWE GW CE1 CE2 CE3 OE
PIPELINED ENABLE
INPUT REGISTERS
ZZ
SLEEP CONTROL
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CY7C1368C
Pin Configurations 100-Pin TQFP Pinout (2-Chip Enable) (AJ version)
Top View CE1 CE2 BWD BWC BWB BWA A VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A A
CY7C1368C (256K x 32)
NC DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQb DQb VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA NC
MODE A A A A A1 A0
NC/72M NC/36M VSS VDD
NC/18M NC
A
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A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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CY7C1368C
Pin Configurations (continued) 100-Pin TQFP Pinout (3-Chip Enable) (A version)
Top View CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A
CY7C1368C (256K x 32)
NC DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA NC
MODE A A A A A1 A0
NC/72M NC/36M VSS VDD
NC/18M
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A A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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CY7C1368C
Pin Descriptions
Pin A0, A1, A TQFP Type Description InputAddress Inputs used to select one of the 256K address locations. Sampled at 37, 36, 32, 33, 34, 35, 44, 45, Synchronous the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and 46, 47, 48, 49, CE3[2] are sampled active. A[1:0] are fed to the two-bit counter. 50, 80, 81, 82, 99, 100, 92 (AJC), 43 (AC) InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes Synchronous to the SRAM. Sampled on the rising edge of CLK. InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge Synchronous of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE). InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This Synchronous signal must be asserted LOW to conduct a byte write. InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation.
BWA, BWB, 93, 94 BWC, BWD GW 88
BWE CLK CE1
87 89 98
InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE1 and CE2 to select/deselect the device. Not available for AJ package version.CE3[2] is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded. InputOutput Enable, asynchronous input, active LOW. Controls the direction of the Asynchronous I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. InputAdvance Input signal, sampled on the rising edge of CLK, active LOW. When Synchronous asserted, it automatically increments the address in a burst cycle. InputAddress Strobe from Processor, sampled on the rising edge of CLK, active Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. InputAddress Strobe from Controller, sampled on the rising edge of CLK, active Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. InputZZ "sleep" Input, active HIGH. When asserted HIGH places the device in a Asynchronous non-time-critical "sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
CE2
97
CE3[2]
92
OE
86
ADV ADSP
83 84
ADSC
85
ZZ
64
DQs
I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, Synchronous is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous 22, 23, 24, 25, clock rise of the read cycle. The direction of the pins is controlled by OE. When OE 28, 29, 52, 53, 56, 57, 58, 59, is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a 62, 63, 68, 69, tri-state condition. 72, 73, 74, 75, 78, 79 15, 41, 65, 91 17, 40, 67, 90 Power Supply Power supply inputs to the core of the device. Ground Ground for the core of the device.
VDD VSS
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Pin Descriptions (continued)
Pin VDDQ VSSQ MODE TQFP 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 31 Type I/O Power Supply I/O Ground InputStatic Description Power supply for the I/O circuitry. Ground for the I/O circuitry. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects. Not internally connected to the die. NC/(18M,36M, 72M, 144M, 288M, 576M, 1G) These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M, 288M, 576M and 1G densities. The CY7C1368C is a double-cycle deselect part. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately after the next clock rise. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The write signals (GW, BWE, and BW[A:D]) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the memory core. If GW is HIGH, then the write operation is controlled by BWE and BW[A:D] signals. The CY7C1368C provides byte write capability that is described in the Write Cycle Description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1368C is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BW[A:D]) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQX is written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain
NC
1, 16, 30, 38, 39, 42, 43(AJC), 51, 66, 80
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1368C supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486TM processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Synchronous Chip Selects CE1, CE2, CE3 and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tco if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported.
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CY7C1368C
unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1368C is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQX inputs. Doing so will tri-state the output drivers. As a safety precaution, DQX are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE.
Interleaved Burst Address Table
(MODE = Floating or VDD) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00
Burst Sequences
The CY7C1368C provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Both read and write burst operations are supported Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported.
Linear Burst Address Table (MODE = GND)
First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
Truth Table[3, 4, 5, 6, 7]
Operation Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down ZZ Mode, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Address Used CE1 CE3 CE2 ZZ ADSP ADSC None None None None None None External External External External External Next H L L L L X L L L L L X X X H X H X L L L L L X X L X L X X H H H H H X L L L L L H L L L L L L X L L H H X L L H H H H L X X L L X X X L L L H ADV X X X X X X X X X X X L WRITE X X X X X X X X L H H H OE X X X X X X L H X L H L CLK L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H DQ Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Q Tri-state D Q Tri-state Q
Notes: 3. X = "Don't Care." H = Logic HIGH, L =Logic LOW. 4. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA, BWB, BWC, BWD), BWE, GW=H. 5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
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Truth Table[3, 4, 5, 6, 7] (continued)
Operation Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used CE1 CE3 CE2 ZZ ADSP ADSC Next X X X L H H Next Next Next Next Current Current Current Current Current Current H H X H X X H H X H X X X X X X X X X X X X X X X X X X X X L L L L L L L L L L X X H X H H X X H X H H H H H H H H H H ADV L L L L L H H H H H H WRITE H H H L L H H H H L L OE H L H X X L H L H X X CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ Tri-state Q Tri-state D D Q Tri-state Q Tri-state D D
Truth Table for Read/Write[3, 4]
Function Read Read Write byte A - (DQA and DQPA) Write byte B - (DQB and DQPB) Write byte C - (DQC and DQPC) Write byte D - (DQD and DQPD) Write all bytes Write all bytes GW H H H H H H H L BWE H L L L L L L X BWA X H L H H H L X BWB X H H L H H L X BWC X H H H L H L X BWD X H H H H L L X
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description sleep mode standby current Device operation to ZZ ZZ recovery time ZZ recovery time ZZ inactive to exit sleep current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 50 2tCYC Unit mA ns ns ns ns
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................... -65C to +150 Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +4.6V Supply Voltage on VDDQ Relative to GND ...... -0.5V to +VDD DC Voltage Applied to Outputs in Tri-State ........................................... -0.5V to VDDQ +0.5V DC Input Voltage ..................................... -0.5V to VDD+0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883,Method 3015) Latch-up Current...................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 3.3V - 5%/+10% VDDQ 2.5V - 5% to VDD
Electrical Characteristics Over the Operating Range[8, 9]
Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[8] Input LOW Voltage[8] Input Leakage Current except ZZ and MODE Input Current of MODE for 3.3V I/O for 2.5V I/O for 3.3V I/O, IOH = -4.0 mA for 2.5V I/O, IOH = -1.0 mA for 3.3V I/O, IOL = 8.0 mA for 2.5V I/O, IOL = 1.0 mA for 3.3V I/O for 2.5V I/O for 3.3V I/O for 2.5V I/O GND VI VDDQ Input = VSS Input = VDD Input Current of ZZ Input = VSS Input = VDD IOZ IDD Output Leakage Current GND VI VDDQ, Output Disabled 4-ns cycle, 250 MHz 5-ns cycle, 200 MHz 6-ns cycle,166 MHz ISB1 Automatic CE Power-down Current--TTL Inputs Automatic CE Power-down Current--CMOS Inputs Automatic CE Power-down Current--CMOS Inputs Automatic CE Power-down Current--TTL Inputs VDD = Max., Device Deselected, VIN VIH or VIN VIL, f = fMAX = 1/tCYC 4-ns cycle, 250 MHz 5-ns cycle, 200 MHz 6-ns cycle,166 MHz -5 VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC -5 30 5 250 220 180 130 120 110 40 mA 2.0 1.7 -0.3 -0.3 -5 -30 5 Test Conditions Min. 3.135 3.135 2.375 2.4 2.0 0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 Max. 3.6 VDD 2.625 Unit V V V V V V V V V V V A A A A A A mA mA mA mA
ISB2
VDD = Max., Device Deselected, All speeds VIN 0.3V or VIN > VDDQ - 0.3V, f=0 VDD = Max., Device Deselected, or VIN 0.3V or VIN > VDDQ - 0.3V, f = fMAX = 1/tCYC VDD = Max., Device Deselected, VIN VIH or VIN VIL, f = 0 4-ns cycle, 250 MHz 5-ns cycle, 200 MHz 6-ns cycle,166 MHz All speeds
ISB3
120 110 100 40
mA
ISB4
mA
Notes: 8. Overshoot: VIH(AC) < VDD+1.5V(Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V(Pulse width less than tCYC/2). 9. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
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Capacitance[10]
Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V 100 TQFP Max. 4 4 4 Unit pF pF pF
Thermal Characteristics[10]
Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 100 TQFP Package 29.41 6.13 Unit C/W C/W
JA JC
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT Z0 = 50 3.3V OUTPUT RL = 50 5 pF INCLUDING JIG AND SCOPE 2.5V Z0 = 50 OUTPUT RL = 50 5 pF VT = 1.25V INCLUDING JIG AND SCOPE R =1538 R = 351 R = 317 VDDQ 10% GND 1 ns ALL INPUT PULSES 90% 90% 10% 1 ns
VT = 1.5V (a)
(b)
R = 1667 VDDQ 10% GND 1 ns
(c)
ALL INPUT PULSES 90% 90% 10% 1 ns
2.5V I/O Test Load
OUTPUT
(a)
(b)
(c)
Note: 10. Tested initially and after any design or process change that may affect these parameters
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Switching Characteristics Over the Operating Range
Parameter tPOWER Clock tCYC tCH tCL Output Times tCO tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Set-up Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tADVH tWEH tDH tCEH Address Hold After CLK Rise ADSP, ADSC Hold After CLK Rise ADV Hold After CLK Rise GW, BWE, BW[A:D] Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.4 0.4 0.4 0.4 0.4 0.4 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Set-up Before CLK Rise ADSC, ADSP Set-up Before CLK Rise ADV Set-up Before CLK Rise GW, OE, BW[A:D] Set-up Before CLK Rise Data Input Set-up Before CLK Rise Chip Enable Set-up Before CLK Rise 1.4 1.4 1.4 1.4 1.4 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low-Z
[12, 13, 14] [15, 16]
-250 Description VDD(Typical) to the first Access Clock Cycle Time Clock HIGH Clock LOW
[11]
-200 Min. 1 5.0 2.0 2.0 2.8 3.0 1.25 1.25 2.8 2.8 1.25 0 2.8 3.0 3.0 3.0 0 1.25 1.25 1.25 Max. Min. 1 6.0 2.4 2.4
-166 Max. Unit ms ns ns ns 3.5 ns ns ns 3.5 3.5 3.5 ns ns ns ns
Min. 1 4.0 1.8 1.8
Max.
1.25 1.25 1.25 0
Clock to High-Z[12, 13, 14] OE LOW to Output Valid OE LOW to Output OE HIGH to Output Low-Z[12, 13, 14] High-Z[12, 13, 14]
Notes: 11. This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above VDD minimum initially before a read or write operation can be initiated. 12. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 13. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 14. This parameter is sampled and not 100% tested. 15. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25 V when VDDQ = 2.5 V. 16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05686 Rev. *F
Page 11 of 18
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CY7C1368C
Switching Waveforms
Read Timing[17]
tCYC
CLK
tCH tADS tADH tCL
ADSP
tADS tADH
ADSC
tAS tAH
ADDRESS
A1
tWES tWEH
A2
A3 Burst continued with new base address
GW, BWE,BW
[A:D] tCES tCEH
Deselect cycle
CE
tADVS tADVH
ADV ADV suspends burst OE
tOEV t CLZ t OEHZ t OELZ tCO tDOH t CHZ
Data Out (Q)
High-Z
Q(A1)
t CO
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
Single READ
BURST READ
Burst wraps around to its initial state
DON'T CARE
UNDEFINED
Note: 17. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05686 Rev. *F
Page 12 of 18
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CY7C1368C
Switching Waveforms (continued)
Write Timing[17, 18]
t CYC
CLK
tCH tADS tADH tCL
ADSP
tADS tADH
ADSC extends burst
tADS tADH
ADSC
tAS tAH
ADDRESS
A1
A2
Byte write signals are ignored for first cycle when ADSP initiates burst
A3
tWES tWEH
BWE, BW[A:D]
tWES tWEH
GW
tCES tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t DS t DH
Data in (D)
High-Z
t OEHZ
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE DON'T CARE UNDEFINED
Extended BURST WRITE
Note: 18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.
Document #: 38-05686 Rev. *F
Page 13 of 18
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CY7C1368C
Switching Waveforms (continued)
Read/Write Timing[17, 19, 20]
tCYC
CLK
tCH tADS tADH tCL
ADSP
ADSC
tAS tAH
ADDRESS BWE, BW[A:D]
A1
A2
A3
tWES tWEH
A4
A5
A6
tCES
tCEH
CE
ADV
OE
tCO tDS tDH tOELZ
Data In (D) Data Out (Q)
High-Z
tCLZ
tOEHZ
D(A3)
D(A5)
D(A6)
High-Z
Q(A1) Back-to-Back READs
Q(A2) Single WRITE DON'T CARE
Q(A4)
Q(A4+1) BURST READ
Q(A4+2)
Q(A4+3) Back-to-Back WRITEs
UNDEFINED
Notes: 19. The data bus (Q) remains in tri-state following a WRITE cycle unless a new read access is initiated by ADSP or ADSC. 20. GW is HIGH.
Document #: 38-05686 Rev. *F
Page 14 of 18
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CY7C1368C
Switching Waveforms (continued)
ZZ Mode Timing [21, 22.]
CLK
t ZZ t ZZREC
ZZ
t ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Notes: 21.Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 22.DQs are in tri-state when exiting ZZ sleep mode.
Document #: 38-05686 Rev. *F
Page 15 of 18
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CY7C1368C
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 166 Ordering Code CY7C1368C-166AXC CY7C1368C-166AJXC CY7C1368C-166AXI CY7C1368C-166AJXI 200 CY7C1368C-200AXC CY7C1368C-200AJXC CY7C1368C-200AXI CY7C1368C-200AJXI 250 CY7C1368C-250AXC CY7C1368C-250AJXC CY7C1368C-250AXI CY7C1368C-250AJXI Package Diagram Part and Package Type Operating Range Commercial
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3 Chip enable) 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (2 Chip enable) 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3 Chip enable) 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (2 Chip enable) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3 Chip enable) 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (2 Chip enable) 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3 Chip enable) 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (2 Chip enable) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3 Chip enable) 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (2 Chip enable) 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3 Chip enable) 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (2 Chip enable)
Industrial
Commercial
Industrial
Commercial
Industrial
Document #: 38-05686 Rev. *F
Page 16 of 18
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CY7C1368C
Package Diagram
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.000.20 14.000.10
100 1 81 80
1.400.05
0.300.08
22.000.20
20.000.10
0.65 TYP.
30 31 50 51
121 (8X)
SEE DETAIL
A
0.20 MAX. 1.60 MAX. 0 MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX.
NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS
0-7
R 0.08 MIN. 0.20 MAX.
0.600.15 0.20 MIN. 1.00 REF.
DETAIL
51-85050-*B
A
Intel and Pentium are registered trademarks, and i486 is a trademark, of Intel Corporation. PowerPC is a registered trademark of IBM. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05686 Rev. *F
0.10
R 0.08 MIN. 0.20 MAX.
Page 17 of 18
(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1368C
Document History Page
Document Title: CY7C1368C 9-Mbit (256K x 32) Pipelined DCD Sync SRAM Document Number: 38-05686 REV. ** *A ECN NO. 286269 323636 Issue Date See ECN See ECN Orig. of Change PCI PCI New data sheet Changed frequency of 225 MHz to 250 MHz Added tCYC to 4.0 ns for 250 MHz Changed JA and JC for TQFP Package from 25 and 9 C/W to 29.41 and 6.13 C/W respectively Added Industrial temperature range Replaced Snooze with Sleep in the ZZ Mode Electrical Characteristics Added 3 chip enable and 2 chip enable for AX and AJX packages in the ordering information table Shaded 250 MHz speed bin in the AC/DC Table and Selection Guide Added Address Expansion pins in the Pin Definition Table Modified VOL, VOH test conditions Corrected VDDQ from (2.5V - 5% to VDD) to (3.3V -5%/+10%) on page# 9 Updated Ordering Information Table Changed ISB2 from 30 to 40 mA Modified test condition in note# 9 from VIH < VDD to VIH < VDD Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Converted from Preliminary to Final Replaced Package Name column with Package Diagram in the Ordering Information table Updated the ordering information Added 2.5VI/O option Updated Ordering Information Table Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Updated the Ordering Information table. Description of Change
*B
332879
See ECN
PCI
*C *D
377095 408725
See ECN See ECN
PCI RXU
*E *F
429278 501828
See ECN See ECN
NXR VKN
Document #: 38-05686 Rev. *F
Page 18 of 18
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